Integrated circuits commonly make use of more than one voltage level. Depending on the technology used, the internal, core structures may operate at one of several low voltage levels (VDD), while the external interface or input/output (I/O) is commonly powered by a higher voltage VDDIO. Typically level shifters are used in beginning stages to shift the voltage level of internal signals up to a higher voltage for I/O purposes. For instance the core voltage signal may be at 1.6 to 2.0 V and be converted to a 4.5 to 5.5V for interfacing to a receiver.
The problem is that the amplification of the signal from the lower core voltage level to the higher voltage interface signal level carries with it a substantial increase in the current in the I/O driver due to the larger loading in the interface, which typically causes elevated noise levels due to voltage overshoot and undershoot, VDDIO droop and ground bounce effects caused by the change in the amount of current passing through inductive, resistive and capacitive components in a short period of time.
The present application seeks to provide a new method of reducing such I/O noise while simultaneously reducing I/O power.